1. Field of the Invention
The invention relates to a method for manufacturing a highly dense integrated circuit using multiple angles tilted from vertical ion implantation to form the source/drain regions of a field effect device.
2. Description of the Prior Art
As the integrated circuit technology increases its device density and attempts to improve its circuit and device performances workers in the field are faced with difficult device design choices. This is particularly the situation in the metal oxide semiconductor field effect transistor, MOSFET integrated circuit device technology.
The lightly doped drain, LDD structure has long been very effectively used in the MOSFET integrated circuit technology to improve device performance. However, as the device density increases there is serious problems involving the use of such a technology. One important factor involves the gate electrode to source/drain overlap. This is a highly preferred structure and is difficult to control with shorter channel width in the more advanced devices. Using the usual vertical ion implantation N- or P- process there is little overlap, even after the drive-in step to activate the implanted ions. Workers in the field have used a longer thermal drive-in or higher temperature to increase the overlap. However, this increases the chance of device punch-through problems.
There is a technology called large tilted angle ion implantation which allows ion implantation to be performed at angles other than the vertical, that is 0.degree.. This technique has been used to make various MOSFET LDD integrated circuit devices. The U.S. Pat. No. 4,771,012 to Yabu et al; U.S. Pat. No. 5,073,514 to Ito et al; U.S. Pat. No. 5,158,901 to Kosa et al and U.S. Pat. No. 5,147,811 all show the use of tilted angle ion implantation to make integrated circuit devices. The publications "1/4 um LATID (LArge-Tilt-angle Implanted Drain) TECHNOLOGY" by T. Hori, published in IEDM 89 pages 777/780 and "GRADED-JUNCTION GATE/N- OVERLAPPED LDD MOSFET STRUCTURES FOR HIGH HOT-CARRIER RELIABILITY" by Y. Okumura et al published in IEEE Transactions on Electron Devices, Vol. 38, No. 12, Dec. 1991, pages 2647-2656 show further use of tilted angle ion implantation. These references all use a single tilted angle ion implantation to improve device performance.
FIG. 1A and 1B illustrate a Prior Art MOSFET LDD structure and the dopant concentration vs junction depth, respectively. The device includes the gate dielectric 12, gate electrode 14, sidewall spacers 20, LDD N- regions, and N+ source/drain regions.
These conventional LDD structures will encounter hot carrier problems when device geometry continues to shrink. That is, when the channel length is decreased the voltage drop across the channel remains the same. For example, 5 volts would increase the electrical field across the channel. This causes hot carrier problems, and transconductance degrades. Namely, the device saturation current decreases with time under operating conditions.
It is therefore a principal object of this invention to increase the gate electrode to source/drain overlap without undue use of thermal drive-in and while maintaining a smaller substrate resistance, Rs.
It is a further object of the invention to increase the gate electrode to source/drain overlap by use of multiple tilted angle ion implantation to cause a gradual change in doping concentration in the overlap which results in a lower electrical field thereby improving hot carrier performance.